1. Field of the Invention
The present invention relates to phase-locked loop (PLL) circuitry.
2. Description of the Prior Art
Currently, in PLL circuits adaptable for use with PLL frequency synthesizers in mobile communications systems or the like, several attempts have been made to shorten the lock-up time in start-up and channel switching events.
One exemplary prior known circuitry is shown in FIG. 12A, wherein two low-pass filters (LPFs) 123 and 124 of different time constants are provided as an LPF known as the "loop filter" which operates to average an output of a charge pump circuit 121 thereby generating a control voltage for use in controlling the frequency of a voltage-controlled oscillator (VCO) circuit 122. This circuit is for shortening the time duration as required for loop stabilization by using only one LPF 123 of less time constant during a frequency transition period and for, after lock-up, switching it to the remaining LPF 124 of greater time constant. Additionally, reference numeral 125 designates a reference signal source; numerals 126 and 127 denote frequency divider circuits for frequency-dividing the outputs of such reference signals source 125 and VCO 122, respectively; and, 128 indicates a phase comparator circuit.
Another prior art circuitry is shown in FIG. 12B, which is designed to reduce the time constant in frequency transition events by use of an LPF 129 of variable time constant.
A still another prior art is known which provides two charge pump circuits as different from each other in ability to supply charge carriers to the loop filter, although such configuration is not illustrated herein. This is configured to cause, when the frequency of an output of the VCO is far from a target frequency also called the "lock frequency," one charge pump circuit of high charge supply ability to effectuate charging and discharging of carriers to and from the loop filter circuit thus allowing the VCO output to rapidly approach the lock frequency or nearby frequencies, and thereafter cause the other charge pump of less charge supply ability to become operative performing precise adjustment of the frequency value.
A further prior art shown in FIG. 12C is such that it includes frequency divider circuits 130, 131 which are provided in addition to the frequency dividers 126, 127 for controlling comparison frequency value to be compared at the phase comparator 128, and a control circuit 132 for controlling the frequency division ratio of them, wherein the comparison frequency value is temporarily higher than the ordinary or standard frequency value when the frequency transition gets started thus shortening the lockup time while attaining a channel switching operations by locking at the standard frequency. Note here that numeral 23 designates an LPF.
However, the scheme switching the aforesaid loop filter circuit or charge pump circuit suffers from difficulty of correct determination as to such switch timing. For this reason, circuitry for generating a signal for the switching increases in scale while at the same time associating the risk of occurrence of fluctuation in frequency due to noises in switching events. Further, the prior art as designed to switch between loop filter circuits should require the use of two different types of loop filter circuits causing its circuit area to increase undesirably. With the prior art that switches to and from the charge pump circuit, the charge supply ability-increased charge pump circuit per se can be sensitive to noises occurring in the PLL system badly behaving to affect the loop filter.
The prior art as designed to temporarily increase the comparison frequency at the beginning of the frequency transition requires use of extra frequency dividers 130, 131 for increasing the comparison frequency. A further problem associated with this prior art is that the PLL system can be disturbed at an instant when the comparison frequency used at the beginning of the transition is switched to standard frequency for the channel switching.